Apparatus and method for adjusting a first electrical signal with respect to a second electrical signal

ABSTRACT

An apparatus for adjusting a first signal with respect to a second signal includes: (a) A first converter receiving the first signal and employing n first converting elements for digitally converting the first signal to at least one first signal element. (b) A second converter coupled with an output, receiving the second signal and employing n second converting elements for digitally converting the second signal to a second representative signal presented at the output. (c) An adjusting element coupled with each of selected of the first converting elements. Each adjusting element is coupled with the output and cooperates with the connected selected element to present a corrected signal element to the output. The output presents an aggregate output signal including contributions from the second representative signal and each corrected signal element. Adjusting is effected by altering at least one corrected first signal element presented to the output.

CROSS REFERENCE TO RELATED APPLICATIONS

The present application is related to U.S. patent application Ser. No. ______ (Attorney Docket TI-61210/DDMO6-019) entitled “APPARATUS AND METHOD FOR COMPENSATING CHANGE IN A TEMPERATURE ASSOCIATED WITH A HOST DEVICE,” filed Aug. 10, 2006, which is assigned to the current assignee hereof.

BACKGROUND OF THE INVENTION

The present invention is directed to treatment of electrical signals, and especially to treatment of electrical signals that represent aspects of temperature.

To reduce temperature drift in an analog circuit, a temperature dependent bias current I(T) may be used. Such bias currents are sometimes expressed as a current (I) function of temperature (T), I(T). The bias current I(T) may be generated from a PTAT (Proportional To Absolute Temperature) current-DAC (Digital to Analog Converter) connected to a CTAT (Complementary To Absolute Temperature) current-DAC. The CTAT current is subtracted from the PTAT current, or vice versa, to generate the desired bias current I(T). The resulting I(T) is injected into a sensitive node of the circuit to be compensated.

Accurate control of absolute value of bias current I(T) at I(T)=0 is critical because it defines the accuracy of the voltage in the sensitive node of the circuit into which the correcting current is injected. This absolute value of bias current I(T) is limited by the matching and resolution of the network of trimmable current sources providing bias current I(T). Providing such a network of trimmable current sources has heretofore required high chip areas and significant power consumption.

There is a need for an apparatus and method for adjusting a first electrical signal with respect to a second electrical signal that can present high resolution for a resulting signal, such as a bias current I(T) for injection as a compensating current into a host device.

SUMMARY OF THE INVENTION

An apparatus for adjusting a first signal with respect to a second signal includes:

(a) A first converter receiving the first signal and employing n first converting elements for digitally converting the first signal to at least one first signal element. (b) A second converter coupled with an output, receiving the second signal and employing n second converting elements for digitally converting the second signal to a second representative signal presented at the output. (c) An adjusting element coupled with each of selected of the first converting elements. Each adjusting element is coupled with the output and cooperates with the connected selected element to present a corrected signal element to the output. The output presents an aggregate output signal including contributions from the second representative signal and each corrected signal element. Adjusting is effected by altering at least one corrected first signal element presented to the output.

A method for adjusting a first electrical signal with respect to a second electrical signal; the method includes the steps of: (a) in no particular order: (1) providing a first converting unit configured for receiving the first electrical signal; the first converting unit having a plurality of n selectively switchable first binary converting elements; and (2) providing a second converting unit configured for receiving the second electrical signal; the second converting unit having a plurality of n selectively switchable second binary converting elements; the second converting unit being coupled with an output locus; (b) providing a respective adjusting element coupled with each of a respective selected element of a plurality of selected elements of the plurality of the n switchable first binary converting elements; each respective adjusting element being coupled with the output locus; (c) in no particular order: (1) operating the plurality of n selectively switchable first binary converting elements to effect digital conversion of the first electrical signal to at least one first representative signal element representing the first electrical signal; (2) operating the plurality of n selectively switchable second binary converting elements for effecting digital conversion of the second electrical signal to a second representative signal representing the second electrical signal; the second converting unit presenting the second representative signal to the output locus; and (3) operating each respective adjusting element in cooperation with the respective connected selected element to present a respective corrected first representative signal element to the output locus; the output locus presenting an aggregate output signal including contributions from the second representative signal and each respective corrected first representative signal element presented to the output locus; and (d) effecting the adjusting by altering at least one corrected first representative signal element presented to the output locus.

It is, therefore, an object of the present invention to provide an apparatus and method for adjusting a first electrical signal with respect to a second electrical signal that can present high resolution for a resulting signal, such as a bias current I(T) for injection as a compensating current into a host device.

Further objects and features of the present invention will be apparent from the following specification and claims when considered in connection with the accompanying drawings, in which like elements are labeled using like reference numerals in the various figures, illustrating the preferred embodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an electrical schematic diagram illustrating prior art generation of a temperature dependent bias current and application of that bias current in an operational amplifier input stage.

FIG. 2 is an electrical schematic diagram illustrating prior art generation of a temperature dependent bias current and application of that bias current in a bandgap circuit.

FIG. 3 is a graphical illustration representing prior art generation of a temperature dependent bias current.

FIG. 4 is an electrical schematic diagram of a prior art apparatus for generating a bias current I(T).

FIG. 5 is an electrical schematic diagram of a first embodiment of an apparatus for generating a bias current I(T) configured according to the present invention.

FIG. 6 is an electrical schematic diagram of a second embodiment of an apparatus for generating a bias current I(T) configured according to the present invention.

FIG. 7 is an electrical schematic diagram of a third embodiment of an apparatus for generating a bias current I(T) configured according to the present invention.

FIG. 8 is an electrical schematic diagram of a fourth embodiment of an apparatus for generating a bias current I(T) configured according to the present invention.

FIG. 9 is a flow chart illustrating the method of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The term “locus” is intended herein to indicate a place, location, locality, locale, point, position, site, spot, volume, juncture, junction or other identifiable location-related zone in one or more dimensions. A locus in a physical apparatus may include, by way of example and not by way of limitation, a corner, intersection, curve, line, area, plane, volume or a portion of any of those features. A locus in an electrical apparatus may include, by way of example and not by way of limitation, a terminal, wire, circuit, circuit trace, circuit board, wiring board, pin, connector, component, collection of components, sub-component or other identifiable location-related area in one or more dimensions. A locus in a flow chart may include, by way of example and not by way of limitation, a juncture, step, site, function, query, response or other aspect, step, increment or an interstice between junctures, steps, sites, functions, queries, responses or other aspects of the flow or method represented by the chart.

FIG. 1 is an electrical schematic diagram illustrating prior art generation of a temperature dependent bias current and application of that bias current in an operational amplifier input stage. In FIG. 1, an operational amplifier input stage 10 includes an NMOS transistor M1 coupled between the operational amplifier (not shown in FIG. 1) and a current source 12 providing a current I_(b2) and an NMOS transistor M2 coupled between the operational amplifier (not shown in FIG. 1) and current source 12. Current source 12 is coupled with a line 14. Input stage 10 also includes a PMOS transistor M3 coupled between a voltage source Vs and a line 16, and a PMOS transistor M4 coupled between voltage source V_(S) and a line 18. A gating signal V_(g1) gates transistors M1, M3. A gating voltage V_(g2) gates transistors M2, M4.

A current source 20 is configured for selectively coupling one of lines 16, 18 with line 14 to impose a zero current bias at a predetermined temperature (0TC) on the selected coupled line 16, 18. A temperature compensating current source 22 is configured for selectively coupling one of line 16, 18 with line 14. Current sources 20, 22 are configured in a manner precluding coupling of both of lines 16, 18 with line 14 at the same time. Current source 22 is employed to inject a bias current I(T) into one of a sensitive drain node 19, 21 in input stage 10 to reduce temperature drift in input stage 10.

Details of current source 22 are also illustrated in FIG. 1. Current source 22 includes a PTAT (Proportional To Absolute Temperature) current source 30 providing a current I_(PTAT), and a CTAT (Complementary To Absolute Temperature) current source 32 providing a current I_(CTAT). Currents I_(PTAT), I_(CTAT) are subtracted, one from the other, to present a resulting bias current I(T). Bias current I(T) is injected at drain nodes 19, 21 of input stage 10. A predetermined temperature T₀ is selected so that bias current I(T₀)=0.

FIG. 2 is an electrical schematic diagram illustrating prior art generation of a temperature dependent bias current and application of that bias current in a bandgap circuit. In FIG. 2, a bandgap reference circuit 40 includes an amplifier 42 having a first input locus 44, a second input locus 46 and an output locus 48. First input locus 44 is coupled with a reference voltage V_(REF) via a resistor 50 and is coupled with a resistor R₂ via a diode connected transistor 52. Second input locus 46 is coupled with reference voltage V_(REF) via a resistor 54 and is coupled with a resistor R₂ via a resistor R₁ and a diode connected transistor 56. A bias current I(T) is injected into bandgap reference circuit 40 at a node 59 common with resistors R₁, R₂. Bias current I(T) is provided from a current source substantially similar to current source 22 (FIG. 1) including a PTAT (Proportional To Absolute Temperature) current source 30 providing a current I_(PTAT), and a CTAT (Complementary To Absolute Temperature) current source 32 providing a current I_(CTAT). Currents I_(PTAT), I_(CTAT) are subtracted, one from the other, to present a resulting bias current I(T) at node 59.

FIG. 3 is a graphical illustration representing prior art generation of a temperature dependent bias current. In FIG. 3, a graphic representation 60 presents current measured on an axis 62 as a function of temperature measured on an axis 64. A curve 66 represents current I_(PTAT) and a second curve 68 represents current I_(CTAT) (FIGS. 1-2). Currents I_(PTAT), I_(CTAT) are subtracted, one from the other, to present a resulting bias current I(T), represented by a curve 70.

Prior art practice selected a predetermined temperature T₀ at an elevated temperature with respect to an expected or nominal operating temperature T₁ for the device being compensated. Prior art practice designed bias current I(T) so that I(T₀)=0. By so selecting temperature T, designers could assure that bias current I(T) would always flow in the same direction over a substantially wide temperature range within the normal temperature operating range expected for the device being compensated. This design choice permitted using a single current mirror to compensate circuits or devices having a negative temperature coefficient, as by mirroring a negative temperature curve −I(T), represented by curve 72 in FIG. 3.

FIG. 4 is an electrical schematic diagram of a prior art apparatus for generating a bias current I(T). In FIG. 4, a temperature dependent current I(T) generator 90 includes a PTAT slope adjusting unit 92, a CTAT slope adjusting unit 94 and a position adjusting unit 96. PTAT slope adjusting unit 92 is embodied in a current DAC (Digital-to-Analog Converter) including NMOS transistors N1, N2, N3, N4, N5, N6 arranged to establish a series of switched current mirrors that cooperate to generate a binary weighted fraction of bias current I_(PTAT). Transistors N2, N3, N4, N5, N6 perform as current sources related with respective bit positions of a digital representation of current I_(PTAT). Transistor N2 performs as a current source related with a 16 (2⁴) bit position of a digital representation of current I_(PTAT). Transistor N3 performs as a current source related with an 8 (2³) bit position of a digital representation of current I_(PTAT). Transistor N4 performs as a current source related with a 4 (2²) bit position of a digital representation of current I_(PTAT). Transistor N5 performs as a current source related with a 2 (2¹) bit position of a digital representation of current I_(PTAT). Transistor N6 performs as a current source related with a 1 (2⁰) bit position of a digital representation of current I_(PTAT). Current mirroring may be established in a ratio RP established by relative W/L (width/length) ratios among transistor N1 and transistors N2, N3, N4, N5, N6.

Transistors or current sources N2, N3, N4, N5, N6 are selectively engaged using switches S2, S3, S4, S5, S6. Cascode devices C2, C3, C4, C5, C6 are added to NMOS transistors N2, N3, N4, N5, N6 in exemplary temperature dependent current generator 90 to improve output resistance of PTAT slope adjusting unit 92. Adding such cascodes is an optional design feature that is a common design practice, so cascode devices C2, C3, C4, C5, C6 will not be discussed further herein.

CTAT slope adjusting unit 94 is embodied in a current DAC (Digital-to-Analog Converter) including NMOS transistors N7, N8, N9, N10, N11, N12 arranged to establish a series of switched current mirrors that cooperate to generate a binary weighted fraction of bias current I_(CTAT). Transistors N8, N9, N10, N11, N12 perform as current sources related with respective bit positions of a digital representation of current I_(CTAT). Transistor N8 performs as a current source related with a 16 (2⁴) bit position of a digital representation of current I_(CTAT). Transistor N9 performs as a current source related with an 8 (2³) bit position of a digital representation of current I_(CTAT). Transistor N10 performs as a current source related with a 4 (2²) bit position of a digital representation of current I_(CTAT). Transistor N11 performs as a current source related with a 2 (2¹) bit position of a digital representation of current I_(CTAT). Transistor N12 performs as a current source related with a 1 (2⁰) bit position of a digital representation of current I_(CTAT). Current mirroring may be established in a ratio RC established by relative W/L (width/length) ratios among transistor N7 and transistors N8, N9, N10, N11, N12.

Transistors or current sources N8, N9, N10, N11, N12 are selectively engaged using switches S8, S9, S10, S11, S12. Cascode devices C8, C9, C10, C11, C12 are added to NMOS transistors N8, N9, N10, N11, N12 in exemplary temperature dependent current generator 90 to improve output resistance of CTAT slope adjusting unit 94. Adding such cascodes is an optional design feature that is a common design practice, so cascode devices C2, C3, C4, C5, C6 will not be discussed further herein.

The same respective switch control signals (not shown in FIG. 4) are applied to control switches S8, S9, S10, S11, S12 as are applied to control switches S2, S3, S4, S5, S6. That is, the same respective switch control signal (not shown in FIG. 4) is applied to activate or deactivate switches S2, S8 together. The same respective switch control signal (not shown in FIG. 4) is applied to activate or deactivate switches S3, S9 together. The same respective switch control signal (not shown in FIG. 4) is applied to activate or deactivate switches S4, S10 together. The same respective switch control signal (not shown in FIG. 4) is applied to activate or deactivate switches S5, S11 together. The same respective switch control signal (not shown in FIG. 4) is applied to activate or deactivate switches S6, S12 together.

Position adjusting unit 94 is embodied in a current DAC (Digital-to-Analog Converter) including PMOS transistors P1, P2, P3, P4, P5, P6, P7, P8. Transistors P1, P2 establish a current mirror 100. Current mirroring may be established in a ratio R1 established by relative W/L (width/length) ratios between transistors P1, P2. Current mirror 100 performs the subtraction I_(PTAT)−I_(CTAT). Position adjusting unit 96 senses the weighted algebraic sum of signals selected by closed switches of switches S2, S3, S4, S5, S6 for provision from NMOS transistors N2, N3, N4, N5, N6 and sources the resulting mirrored current to an output node 98. Transistors P3, P4, P5, P6, P7, P8 establish a series of switched current mirrors that cooperate to generate a binary weighted fraction of subtraction I_(PTAT)−I_(CTAT). Transistors P3, P4, P5, P6, P7, P8 are selectively engaged using switches S14, S15, S16, S17, S18, S19.

NMOS transistors N8, N9, N10, N11, N12 are also connected to output node 98 by selected closed switches of switches S8, S9, S10, S11, S12.

Ignoring transistors P3, P4, P5, P6, P7, P8 for the moment and assuming that transistors P1, P2 have the same W/L, width and length (i.e., assuming that current mirror 100 exhibits a 1:1 mirroring ratio), the output current I(T) at output locus 98 would be:

I(T)=I _(PTAT)(T)·(2⁰ ·S ₂+2⁻¹ ·S ₃+2⁻² ·S ₄+2⁻³ ·S ₅+2⁻⁴ ·S ₆)−I _(CTAT)(T)·(2⁰ ·S ₈+2⁻¹ ·S ₉+2⁻² ·S ₁₀+2⁻³ ·S ₁₁+2⁻⁴ ·S ₁₂)  [1]

Where S₂=S₈; S₃=S₉; S₄=S₁₀; S₅=S₁₁; S₆=S₁₂;

and W/L(P1)=W/L(P2)

The coefficients S₂-S₁₂ are Boolean values (“0” or “1”) depending on the switch state of each of respective switches S2, S3, S4, S5, S6, S8, S9, S10, S11, S12. If the value of a coefficient S_(X) in Equation [1] is “1”, then switch S_(X) is closed (i.e., conducting) and the corresponding current segment contributes both a PTAT and a CTAT current to the output signal I(T) at output locus 98 (because S₂=S₈; S₃=S₉; S₄=S₁₀; S₅=S₁₁; S₆=S₁₂). If the value of a coefficient S_(X) in Equation [1] is “0”, then switch S_(X) is open (i.e., nonconducting) and the corresponding current segment contributes no current to the output signal I(T) at output locus 98.

A desired design goal is to force I(T) to a zero value at a predetermined temperature T₀. In Equation [1], this condition is only true if the condition I_(PTAT)(T₀)=I_(CTAT)(T₀) holds, as occurs for example at temperature T₀ in FIG. 3. The desired result may be achieved by individually trimming I_(PTAT) current source 30 and I_(PTAT) current source 32 (FIG. 1) in a package final test at temperature T₀.

In a typical implementation, I_(PTAT) current source 30 may adjusted (e.g., by trimming) in such a way that I(T₀)=0. Temperature dependent current generator 90 (FIG. 4) permits adjustment of contribution by I_(PTAT) current to output current I(T) at output locus 98 using position adjust unit 98 embodied in a binary weighted switchable current mirror P1, P2-P8. Positions of switches S14-S19 are chosen to achieve the condition I(T₀)=0. This desired condition may be verified indirectly (e.g., requiring no change in output voltage in case of a bandgap circuit). The overall output current I(T) appearing at output locus 98 is:

I(T)=I _(PTAT)(T)·x _(—) pos·(2⁰ ·S ₂+2⁻¹ ·S ₃+2⁻² ·S ₄+2⁻³ ·S ₅+2⁻⁴ ·S ₆)−I _(CTAT)(T)·(2⁰ ·S ₈+2⁻¹ ·S ₉+2⁻² ·S ₁₀+2⁻³ ·S ₁₁+2⁻⁴ ·S ₁₂)  [2]

Where S₂=S₈; S₃=S₉; S₄=S₁₀; S₅=S₁₁; S₆=S₁₂;

and x_pos=(2⁻²+2⁻¹·S₁₄+2⁻²·S₁₅+2⁻³·S₁₆+2⁻⁴·S₁₇+2⁻⁶·S₁₉)

Equation [2] illustrates that I(T₀)=0 can be achieved even if I_(PTAT)(T₀)≠I_(CTAT)(T₀) by properly selecting coefficients S₁₄-S₁₉. This selection of coefficients S₁₄-S₁₉ may be effected during a “test at first temperature T₀” procedure. After the first test, a second test may be conducted at a significantly different temperature T₁ (e.g. nominal or expected operating temperature of the device being compensated (not shown in FIG. 4; see FIG. 3). Given test results at two temperatures, an actual temperature drift may be estimated. By way of example and not by way of limitation, in a bandgap device temperature drift may be determined by tracking a reference output voltage.

Temperature drift may be compensated by choosing a binary weighted I(T) sum at output locus 98 of temperature dependent current generator 90 that is appropriate to shift the reference output voltage to a target value and injecting this I(T) into the core circuit of the device being compensated. This may be effected using temperature dependent generating circuit 90 by a unique value for the five data input bits at switched S2-S6/S8-S12 in slope adjust units 92, 94 (recall that S2=S8, S3=S9, S4=S10, S5=S11, S6=S12). In terms of Equation [2] this requires choosing coefficients S₂-S₆/S₈-S₁₂ to adjust I(T₁) to the desired value. The second test described above may be independent from the first test, so there is no requirement for tracking of die identification or tracking previous test data. Test implementation is therefore relatively cheap and easy. In single ended architectures (e.g., bandgap devices), bias current I(T) is provided also with the opposite temperature coefficient. For differential architectures, such as operational amplifiers, one temperature coefficient (e.g. positive) for bias current I(T) is likely sufficient because the compensating bias current I(T) may be injected on either side of the differential path to correct both positive and negative residual temperature coefficients.

Prior art temperature dependent current generator 90 has shortcomings. PTAT and CTAT current sources, transistors N1-N12 are subject to mismatch variations during manufacture. This mismatch likelihood is not included in Equation [2]. A result of such mismatches is a reduction in absolute accuracy of bias current I(T). The variations can differ among any of transistors N2, N3, N4, N5, N6 and among any of transistors N8, N9, N10, N11, N12, so that accuracy of the binary digital representation of bias current I(T) presented at output locus 98 is code dependent (i.e., depends on values of S₂-S₆/S₈-S₁₂). By way of example and not by way of limitation, transistor N2 may have a V_(t) (threshold voltage) mismatch with respect to V_(t) of transistor N1. Such a mismatch can result in an I_(D) (drain current) mismatch Ierr₂ between transistors N1, N2. This mismatch between transistors N1, N2 may be expressed as:

I _(D)(N2)=I _(D)(N1)·(1+Ierr ₂)  [3]

Mismatch Ierr₂ can be positive or negative and strongly depends on technology and parameterization of transistors N1, N2. By way of further example and not by way of limitation, a similar condition may exist with respect to transistors N7, N8 so that

I _(D)(N8)=I _(D)(N7)·(1+Ierr ₈)  [4]

By way of still further example and not by way of limitation, transistor N3 can have a V_(t) mismatch with respect to transistor N1 which can be just opposite to the mismatch with respect to transistors N1, N2. This may occur because statistical mismatch among transistors is uncorrelated. In such a case,

I _(D)(N3)=I _(D)(N1)·(1+Ierr ₃)  [5]

Mismatch Ierr₃ can be positive or negative, and in a worst case Ierr₃=−Ierr₂. One skilled in the art of transistor circuit design may recognize that similar relations may hold for other transistors N4, N5, N6, N9-N12 with all errors uncorrelated. The corrected Equation [2] for I(T) results:

$\begin{matrix} {\begin{matrix} {{I(T)} = {{I_{PTAT}(T)} \cdot {x\_ pos} \cdot \left( {{2^{0} \cdot S_{2} \cdot \left( {1 + {{Ierr}\; 2}} \right)} + {2^{- 1} \cdot S_{3} \cdot}} \right.}} \\ {{\left( {1 + {{Ierr}\; 3}} \right) + {2^{- 2} \cdot S_{4} \cdot \left( {1 + {{Ierr}\; 4}} \right)} + {2^{- 3} \cdot S_{5} \cdot}}} \\ {\left. {\left( {1 + {{Ierr}\; 5}} \right) + {2^{- 4} \cdot S_{6} \cdot \left( {1 + {{Ierr}\; 6}} \right)}} \right) - {{I_{CTAT}(T)} \cdot \left( {2^{0} \cdot S_{8} \cdot} \right.}} \\ {{\left( {1 + {{Ierr}\; 8}} \right) + {2^{- 1} \cdot S_{9} \cdot \left( {1 + {{Ierr}\; 9}} \right)} + {2^{- 1} \cdot S_{9} \cdot \left( {1 + {{Ierr}\; 9}} \right)} +}} \\ {{{2^{- 2} \cdot S_{10} \cdot \left( {1 + {{Ierr}\; 10}} \right)} + {2^{- 3} \cdot S_{11} \cdot \left( {1 + {{Ierr}\; 11}} \right)} +}} \\ \left. {2^{- 4} \cdot S_{12} \cdot \left( {1 + {{Ierr}\; 12}} \right)} \right) \end{matrix}{Where}{{S_{2} = S_{8}};{S_{3} = S_{9}};{S_{4} = S_{10}};{S_{5} = S_{11}};{S_{6} = S_{12}};}{and}\begin{matrix} {{x\_ pos} = \left( {2^{- 2} + {2^{- 1} \cdot S_{14}} + {2^{- 2} \cdot S_{15}} +} \right.} \\ \left. {{2^{- 3} \cdot S_{16}} + {2^{- 4} \cdot S_{17}} + {2^{- 5} \cdot S_{18}} + {2^{- 6} \cdot S_{19}}} \right) \end{matrix}} & \lbrack 6\rbrack \end{matrix}$

Because all mismatches Ierr_(x) are uncorrelated, all of the mismatch coefficients may have different magnitudes and cannot be corrected simultaneously by one set of coefficients S₁₄-S₁₉ in x_pos. That means the final value of bias current at temperature T₀, I(T₀), is code-dependent (i.e. depends on the values of coefficients S₂-S₆/S₈-S₁₂). One skilled in the art of transistor circuit design may see that the resulting errors in absolute value of bias current I(T) in temperature dependent current generator 90 are too large for high precision circuits such as bandgap references with better than 0.01% initial accuracy.

FIG. 5 is an electrical schematic diagram of a first embodiment of an apparatus for generating a bias current I(T) configured according to the present invention. The present invention overcomes limited accuracy provided with temperature dependent current generator 90 by trimming each current DAC bit segment individually. In FIG. 5, a temperature dependent current I(T) generator 110 includes a PTAT slope adjusting unit 112, a CTAT slope adjusting unit 114 and a position adjusting unit 116. PTAT slope adjusting unit 112 is similar to PTAT slope adjusting unit 92 (FIG. 4). PTAT slope adjusting unit 112 is embodied in a current DAC (Digital-to-Analog Converter) including NMOS transistors N1, N2, N3, N4, N5, N6 arranged to establish a series of switched current mirrors that cooperate to generate a binary weighted fraction of bias current I_(PTAT). Transistors N2, N3, N4, N5, N6 perform as current sources related with respective bit positions of a digital representation of current I_(PTAT). Transistor N2 performs as a current source related with a 16 (2⁴) bit position of a digital representation of current I_(PTAT). Transistor N3 performs as a current source related with an 8 (2³) bit position of a digital representation of current I_(PTAT). Transistor N4 performs as a current source related with a 4 (2²) bit position of a digital representation of current I_(PTAT). Transistor N5 performs as a current source related with a 2 (2¹) bit position of a digital representation of current I_(PTAT). Transistor N6 performs as a current source related with a 1 (2⁰) bit position of a digital representation of current I_(PTAT). Current mirroring may be established in a ratio RP established by relative W/L (width/length) ratios among transistor N1 and transistors N2, N3, N4, N5, N6.

Transistors or current sources N2, N3, N4, N5, N6 are selectively engaged using switches S2, S3, S4, S5, S6. Cascode devices C2, C3, C4, C5, C6 are added to NMOS transistors N2, N3, N4, N5, N6 in exemplary temperature dependent current generator 110 to improve output resistance of PTAT slope adjusting unit 112. Adding such cascodes is an optional design feature that is a common design practice, so cascode devices C2, C3, C4, C5, C6 will not be discussed further herein.

CTAT slope adjusting unit 114 is similar to CTAT slope adjusting unit 94 (FIG. 4). CTAT slope adjusting unit 114 is embodied in a current DAC (Digital-to-Analog Converter) including NMOS transistors N7, N8, N9, N10, N11, N12 arranged to establish a series of switched current mirrors that cooperate to generate a binary weighted fraction of bias current I_(CTAT). Transistors N8, N9, N10, N11, N12 perform as current sources related with respective bit positions of a digital representation of current I_(CTAT). Transistor N8 performs as a current source related with a 16 (2⁴) bit position of a digital representation of current I_(CTAT). Transistor N9 performs as a current source related with an 8 (2³) bit position of a digital representation of current I_(CTAT). Transistor N10 performs as a current source related with a 4 (2²) bit position of a digital representation of current I_(CTAT). Transistor N11 performs as a current source related with a 2 (2¹) bit position of a digital representation of current I_(CTAT). Transistor N12 performs as a current source related with a 1 (2⁰) bit position of a digital representation of current I_(CTAT). Current mirroring may be established in a ratio RC established by relative W/L (width/length) ratios among transistor N7 and transistors N8, N9, N10, N11, N12.

Transistors or current sources N8, N9, N10, N11, N12 are selectively engaged using switches S8, S9, S10, S11, S12. Cascode devices C8, C9, C10, C11, C12 are added to NMOS transistors N8, N9, N1, N11, N12 in exemplary temperature dependent current generator 10 to improve output resistance of CTAT slope adjusting unit 114. Adding such cascodes is an optional design feature that is a common design practice, so cascode devices C2, C3, C4, C5, C6 will not be discussed further herein.

The same respective switch control signals (not shown in FIG. 5) are applied to control switches S8, S9, S10, S11, S12 as are applied to control switches S2, S3, S4, S5, S6. That is, the same respective switch control signal (not shown in FIG. 5) is applied to activate or deactivate switches S2, S8 together. The same respective switch control signal (not shown in FIG. 5) is applied to activate or deactivate switches S3, S9 together. The same respective switch control signal (not shown in FIG. 5) is applied to activate or deactivate switches S4, S10 together. The same respective switch control signal (not shown in FIG. 5) is applied to activate or deactivate switches S5, S11 together. The same respective switch control signal (not shown in FIG. 5) is applied to activate or deactivate switches S6, S12 together.

Position adjusting unit 116 is embodied in a plurality of position adjusting arrays 120, 122, 124, 126, 128. Each of position adjusting arrays 120, 122, 124, 126, 128 adjusts a respective individual bit output of PTAT slope adjusting unit 112. In order to simplify FIG. 5, details are illustrated only for position adjusting arrays 120, 122, 128.

Position adjusting array 120 is embodied in a current DAC (Digital-to-Analog Converter) including PMOS transistors P11, P12, P13, P14, P15, P16, P17, P18. Transistors P11, P12 establish a current mirror 121. Current mirroring may be established in a ratio R1 established by relative W/L (width/length) ratios between transistors P11, P12. Current mirror 121 performs current mirroring of output from transistor N2 via switch S2 of PTAT adjusting unit 112 representing a current source related with a 16 (2⁴) bit position of a digital representation of current I_(PTAT) to transistors P13, P14, P15, P16, P17, P18. Position adjusting array 120 presents a representation of current contribution from transistor N2 in a contributing current signal I_(OUT1) to an output locus 130. Transistor P13 presents a current contribution representing a 16 (2⁴) bit position of a digital representation of current contribution from transistor N2. Transistor P14 presents a current contribution representing an 8 (2³) bit position of a digital representation of current contribution from transistor N2. Transistor P15 presents a current contribution representing a 4 (2²) bit position of a digital representation of current contribution from transistor N2. Transistor P16 presents a current contribution representing a 2 (2¹) bit position of a digital representation of current from transistor N2. Transistor P17 presents a current contribution representing a 1 (2⁰) bit position of a digital representation of current contribution from transistor N2. Transistor P18 presents a current contribution representing a 0.5 (2⁻¹) bit position of a digital representation of current contribution from transistor N2.

Position adjusting array 122 is embodied in a current DAC (Digital-to-Analog Converter) including PMOS transistors P21, P22, P23, P24, P25, P26, P27. Transistors P21, P22 establish a current mirror 123. Current mirroring may be established in a ratio R2 established by relative W/L (width/length) ratios between transistors P21, P22. Current mirror 123 performs current mirroring of output from transistor N3 via switch S3 of PTAT adjusting unit 112 representing a current source related with a 8 (2³) bit position of a digital representation of current I_(PTAT) to transistors P23, P24, P25, P26, P27. Position adjusting array 122 presents a representation of current contribution from transistor N3 in a contributing current signal I_(OUT2) to output locus 130. Transistor P23 presents a current contribution representing an 8 (2³) bit position of a digital representation of current contribution from transistor N3. Transistor P24 presents a current contribution representing a 4 (2²) bit position of a digital representation of current contribution from transistor N3. Transistor P25 presents a current contribution representing a 2 (2¹) bit position of a digital representation of current from transistor N3. Transistor P26 presents a current contribution representing a 1 (2⁰) bit position of a digital representation of current contribution from transistor N3. Transistor P27 presents a current contribution representing a 0.5 (2⁻¹) bit position of a digital representation of current contribution from transistor N3.

Position adjusting array 124 (not shown in detail in FIG. 5) presents a representation of current contribution from transistor N4 in a contributing current signal (not shown in FIG. 5) to output locus 130. Position adjusting array 126 (not shown in detail in FIG. 5) presents a representation of current contribution from transistor N5 in a contributing current signal (not shown in FIG. 5) to output locus 130. Position adjusting arrays 124, 126 are preferably configured similar to position arrays 102, 122 providing an array of transistors, each of which may be employed for contributing a current contribution relating to a respective bit position of a digital representation from PTAT slope adjusting unit 112. Each respective current contribution is applied to output locus 130.

Position adjusting array 128 is embodied in a current DAC (Digital-to-Analog Converter) including PMOS transistors Pn1, Pn2, Pn3, Pn4, Pn5. Transistors Pn1, Pn2 establish a current mirror 129. Current mirroring may be established in a ratio Rn established by relative W/L (width/length) ratios between transistors Pn1, Pn2. Current mirror 129 performs current mirroring of output from transistor N6 via switch S6 of PTAT adjusting unit 112 representing a current source related with a 1 (2⁰) bit position of a digital representation of current I_(PTAT) to transistors Pn1, Pn2, Pn3, Pn4, Pn5. Position adjusting array 128 presents a representation of current contribution from transistor N6 in a contributing current signal I_(OUTn) to output locus 130. Transistor Pn3 presents a current contribution representing an 2 (2¹) bit position of a digital representation of current contribution from transistor N6. Transistor Pn4 presents a current contribution representing a 1 (2⁰) bit position of a digital representation of current contribution from transistor N6. Transistor Pn5 presents a current contribution representing a 0.5 (2⁻¹) bit position of a digital representation of current contribution from transistor N6.

The indicator “n” is employed to signify that there can be any number of position adjusting arrays in temperature dependent current generator 110. The inclusion of five position adjusting arrays 120, 122, 124, 126, 128 in FIG. 5 is illustrative only and does not constitute any limitation regarding the number of position adjusting arrays that may be included in the temperature dependent current generator of the present invention.

Provision of a plurality of position adjusting arrays 120, 122, 124, 126, 128 coupled for individual treatment of respective bit positions of PTAT slope adjusting unit 112 permits separate balancing of the current contribution of each individual PTAT-CTAT transistor pair N2-N8, N3-N9, N4-N10, N5-N11, N6-N12. Resolution of the various position adjust arrays 120, 122, 124, 126, 128 can be reduced as the current of a respective transistor pair Nx-Ny decreases with larger x-y (e.g., current in transistor pair N3-N9 is smaller than current in transistor pair N2-N8). This is indicated by labeling position adjust array 120 as MSB (Most Significant Bit), labeling position adjust array 122 as MSB−1 (Most Significant Bit minus 1), labeling position adjust array 124 as MSB−1 (Most Significant Bit minus 2), labeling position adjust array 126 as MSB−3 (Most Significant Bit minus 3) and labeling position adjust array 128 as LSB (Least Significant Bit).

Temperature dependent current generator 110 permits separately compensating a mismatch in each individual PTAT-CTAT segment by selecting the coefficients for each of switches coupled with a PMOS transistor in a position adjust array 120, 122, 124, 126, 128. The coefficients are Boolean representations of the open (coefficient “0”) or closed (coefficient “1”) orientation of a respective switch. The corrected Equation [2] for I(T) as applied to temperature dependent current generator 110 results:

$\begin{matrix} {\begin{matrix} {{I(T)} = {{I_{PTAT}(T)} \cdot \left( {{2^{0} \cdot S_{2} \cdot {x\_ pos}_{2} \cdot \left( {1 + {{Ierr}\; 2}} \right)} +} \right.}} \\ {{{2^{- 1} \cdot S_{3} \cdot {x\_ pos}_{3} \cdot \left( {1 + {{Ierr}\; 3}} \right)} + {2^{- 2} \cdot S_{4} \cdot {x\_ pos}_{4} \cdot}}} \\ {{\left( {1 + {{Ierr}\; 4}} \right) + {2^{- 3} \cdot S_{5} \cdot {x\_ pos}_{5} \cdot \left( {1 + {{Ierr}\; 5}} \right)} +}} \\ {\left. {2^{- 4} \cdot S_{6} \cdot {x\_ pos}_{6} \cdot \left( {1 + {{Ierr}\; 6}} \right)} \right) - {{I_{CTAT}(T)} \cdot}} \\ {\left( {{2^{0} \cdot S_{8} \cdot \left( {1 + {{Ierr}\; 8}} \right)} + {2^{- 1} \cdot S_{9} \cdot \left( {1 + {{Ierr}\; 9}} \right)} +} \right.} \\ {{{2^{- 2} \cdot S_{10} \cdot \left( {1 + {{Ierr}\; 10}} \right)} + {2^{- 3} \cdot S_{11} \cdot \left( {1 + {{Ierr}\; 11}} \right)} +}} \\ \left. {2^{- 4} \cdot S_{12} \cdot \left( {1 + {{Ierr}\; 12}} \right)} \right) \end{matrix}{Where}{{S_{2} = S_{8}};{S_{3} = S_{9}};{S_{4} = S_{10}};{S_{5} = S_{11}};{S_{6} = S_{12}};}{and}\begin{matrix} {{x\_ pos}_{z} = \left( {2^{- 2} + {2^{- 1} \cdot {SP}_{z\; 1}} + {2^{- 2} \cdot {SP}_{z\; 2}} +} \right.} \\ \left. {{2^{- 3} \cdot {SP}_{z\; 3}} + {2^{- 4} \cdot {SP}_{z\; 4}} + {{2^{- 5} \cdot {SP}_{{z\; 5} +}}{2^{- 6} \cdot {SP}_{z\; 6}}}} \right) \end{matrix}} & \lbrack 7\rbrack \end{matrix}$

A notation SP_(xn) indicates a Boolean coefficient for a switch coupled with a PMOS transistor PZN, such as a coefficient for switch S13 coupled with PMOS transistor P13 in position adjust array 122.

From Equation [7] one may observe that each individual mismatch Ierrn in a respective PTAT-CTAT transistor pair N2-N8, N3-N9, N4-N10, N5-N11, N6-N12 can be compensated by an individual trimming network x_pos_(z). For determination of appropriate coefficients for each respective trimming network x_pos_(z) one may set all other switches S_(j), with j≠z, to a nonconducting state and sweep through all coefficient combinations SP_(iy) until the output value approaches desired value (e.g., a desired bandgap output).

FIG. 6 is an electrical schematic diagram of a second embodiment of an apparatus for generating a bias current I(T) configured according to the present invention. In FIG. 6, a temperature dependent current I(T) generator 210 includes a PTAT slope adjusting unit 212, a CTAT slope adjusting unit 214 and a position adjusting unit 216. PTAT slope adjusting unit 212 is substantially the same as PTAT slope adjusting units 92, 112 (FIGS. 4 & 5). In order to avoid prolixity, PTAT slope adjust unit 212 will not be further described herein. CTAT slope adjusting unit 214 is substantially the same as CTAT slope adjusting units 94, 114 (FIGS. 4 & 5). In order to avoid prolixity, CTAT slope adjust unit 214 will not be further described herein.

Position adjusting unit 216 is embodied in a plurality of position adjusting arrays 220, 222, 224, 226, 228. Each of position adjusting arrays 220, 222, 224, 226, 228 adjusts a respective individual bit output of PTAT slope adjusting unit 212 substantially as position adjusting arrays 120, 122, 124, 126, 128 adjust respective individual bit outputs of PTAT slope adjusting unit 112 (FIG. 5). A distinction between temperature dependent current generators 110, 210 is that gate bias for each of position adjusting arrays 220, 222, 224, 226, 228 is provided from a separate or external voltage generator at a gate bias input locus 232. The gate bias voltage may preferably be generated, by way of example and not by way of limitation, from a PTAT type circuit similar to the IPTAT input provided for PTAT slope adjusting unit 212 so that the gate bias voltage may provide a PTAT temperature coefficient for operation of each of position adjusting arrays 220, 222, 224, 226, 228. Other than providing an externally generated gate bias voltage for each of position adjusting arrays 220, 222, 224, 226, 228 at gate bias input locus 232, temperature dependent current I(T) generator 210 operates substantially the same as temperature dependent current generator 112 (FIG. 5).

FIG. 7 is an electrical schematic diagram of a third embodiment of an apparatus for generating a bias current I(T) configured according to the present invention. In FIG. 7, a temperature dependent current I(T) generator 310 includes a PTAT slope adjusting unit 312, a CTAT slope adjusting unit 314 and a position adjusting unit 316. PTAT slope adjusting unit 312 is substantially the same as PTAT slope adjusting units 92, 112, 212 (FIGS. 4, 5 & 6). In order to avoid prolixity, PTAT slope adjust unit 312 will not be further described herein. CTAT slope adjusting unit 314 is substantially the same as CTAT slope adjusting units 94, 114, 214 (FIGS. 4, 5 & 6). In order to avoid prolixity, CTAT slope adjust unit 314 will not be further described herein.

Position adjusting unit 316 is embodied in a plurality of position adjusting arrays 320, 320A, 322, 322A, 324, 326, 328. Gate bias voltages GATE BIAS 1, GATE BIAS 2 are provided from separate or external voltage generators at a gate bias input loci 332, 334. GATE BIAS 1 is provided for biasing transistors P13, P14, P15, P16, P17 in position adjusting array 320 and is provided for biasing transistors P23, P24, P25, P26 in position adjusting array 322. GATE BIAS 2 is provided for biasing transistors P18, P19, P110 in position adjusting array 320A, is provided for biasing transistors P27, P28, P29 in position adjusting array 322 and is provided for biasing transistors Pn3, Pn4, Pn5 in position adjusting array 328.

Multiple externally generated gate voltages may be used to provide cascaded position adjusting DAC arrays with overlapping dynamic ranges. By way of example and not by way of limitation, in FIG. 7, smaller currents from position adjusting arrays based on input GATE BIAS 2 are used to interpolate between current values generated by the position adjusting arrays based on input GATE BIAS 1.

Using different gate bias voltages GATE BIAS 1, GATE BIAS 2 with transistors addressing overlapping bit contributions to output currents presented at output locus 330 permits interpolation of a plurality of contributing I(T) currents with overlapping dynamic range. Thus, temperature dependent current generator 310 provides for position adjusting arrays 320, 320A to include a current mirror 321 established by transistors P11, P12. Current mirroring may be established in a ratio R1 established by relative W/L (width/length) ratios between transistors P11, P12. Current mirror 321 performs current mirroring of output from transistor N2 via switch S2 of PTAT adjusting unit 312 representing a current source related with a 16 (2⁴) bit position of a digital representation of current I_(PTAT) to transistors P13, P14, P15, P16, P17, P18, P19, P110. Position adjusting arrays 320, 320A present a representation of current contribution from transistor N2 in a contributing current signal I_(OUT1) to an output locus 330. Transistor P13 presents a current contribution representing a 16 (2⁴) bit position of a digital representation of current contribution from transistor N2. Transistor P14 presents a current contribution representing an 8 (2³) bit position of a digital representation of current contribution from transistor N2. Transistor P15 presents a current contribution representing a 4 (2²) bit position of a digital representation of current contribution from transistor N2. Transistor P16 presents a current contribution representing a 2 (2¹) bit position of a digital representation of current contribution from transistor N2. Transistor P17 presents a current contribution representing a 1 (2⁰) bit position of a digital representation of current contribution from transistor N2. Transistor P18 in position adjustment array 320A presents a current contribution representing a 4 (2²) bit position of a digital representation of current contribution from transistor N2. Transistor P19 in position adjustment array 320A presents a current contribution representing a 2 (2¹) bit position of a digital representation of current contribution from transistor N2. Transistor P110 in position adjustment array 320A presents a current contribution representing a 1 (2⁰) bit position of a digital representation of current contribution from transistor N2. Transistors P18, P19, P110 in position adjustment array 320A overlap current contributions by transistors P15, P16, P17 in position adjustment array 320. By providing different gate bias signals GATE BIAS 1, GATE BIAS 2 to position adjustment arrays 320, 320A, interpolation may be effected regarding current contributions representing a 4 (2²) bit position (transistors P15, P18), a 2 (2¹) bit position (transistors P16, P19) and a 1 (2⁰) bit position (transistors P17, P110) of a digital representation of current contribution from transistor N2.

Temperature dependent current generator 310 also provides for position adjusting arrays 322, 322A to include a current mirror 323 established by transistors P21, P22. Current mirroring may be established in a ratio R2 established by relative W/L (width/length) ratios between transistors P21, P22. Current mirror 323 performs current mirroring of output from transistor N3 via switch S3 of PTAT adjusting unit 312 representing a current source related with an 8 (2³) bit position of a digital representation of current I_(PTAT) to transistors P23, P24, P25, P26, P27, P28, P29. Position adjusting arrays 322, 322A present a representation of current contribution from transistor N3 in a contributing current signal I_(OUT2) to an output locus 330. Transistor P23 presents a current contribution representing an 8 (2³) bit position of a digital representation of current contribution from transistor N3. Transistor P24 presents a current contribution representing a 4 (2²) bit position of a digital representation of current contribution from transistor N3. Transistor P25 presents a current contribution representing a 2 (2¹) bit position of a digital representation of current contribution from transistor N3. Transistor P26 presents a current contribution representing a 1 (2⁰) bit position of a digital representation of current contribution from transistor N3. Transistor P27 in position adjustment array 322A presents a current contribution representing a 4 (2²) bit position of a digital representation of current contribution from transistor N3. Transistor P28 in position adjustment array 322A presents a current contribution representing a 2 (2¹) bit position of a digital representation of current contribution from transistor N3. Transistor P29 in position adjustment array 322A presents a current contribution representing a 1 (2⁰) bit position of a digital representation of current contribution from transistor N3. Transistors P27, P28, P29 in position adjustment array 322A overlap current contributions by transistors P24, P25, P26 in position adjustment array 320. By providing different gate bias signals GATE BIAS 1, GATE BIAS 2 to position adjustment arrays 322, 322A, interpolation may be effected regarding current contributions representing a 4 (2²) bit position (transistors P24, P27), a 2 (2¹) bit position (transistors P25, P28) and a 1 (2⁰) bit position (transistors P26, P29) of a digital representation of current contribution from transistor N3.

Details of construction relation to position adjustment arrays 324, 326 are not illustrated in FIG. 7. One skilled in the art of transistor circuit design may understand how position adjustment arrays 324, 326 may be advantageously configured using the teachings of the present invention. Position adjustment array 328 is illustrated using only one gate bias voltage GATE BIAS 2. One skilled in the art of transistor circuit design may understand how position adjustment array 328 may be advantageously configured using the teachings of the present invention.

Other than providing a plurality of externally generated gate bias voltage for selected position adjusting arrays 320, 320A, 322, 322A, 324, 326, 328 at gate bias input loci 332, 334, temperature dependent current I(T) generator 310 operates substantially the same as temperature dependent current generators 112, 212 (FIGS. 5 & 6).

FIG. 8 is an electrical schematic diagram of a fourth embodiment of an apparatus for generating a bias current I(T) configured according to the present invention. In FIG. 8, a temperature dependent current I(T) generator 410 includes a PTAT slope adjusting unit 412, a CTAT slope adjusting unit 414 and a position adjusting unit 416. PTAT slope adjusting unit 412 is substantially the same as PTAT slope adjusting units 92, 112, 212, 312 (FIGS. 4, 5, 6 & 7). In order to avoid prolixity, PTAT slope adjust unit 412 will not be further described herein. CTAT slope adjusting unit 414 is substantially the same as CTAT slope adjusting units 94, 114, 214, 314 (FIGS. 4, 5, 6 & 7). In order to avoid prolixity, CTAT slope adjust unit 414 will not be further described herein.

Position adjusting unit 416 is embodied in a plurality of position adjusting arrays 320, 320A, 322, 322A, 324, 326, 328 arranged substantially as described in connection with temperature dependent current generator 310 (FIG. 7). Gate bias voltages GATE BIAS 1, GATE BIAS 2 are provided from separate or external voltage generators at a gate bias input loci 432, 434.

Position adjusting unit 416 includes a single PTAT summing current mirror 421 established by transistors P11, P12 in position adjusting arrays 420, 420A. Current mirroring may be established in a ratio R1 established by relative W/L (width/length) ratios between transistors P11, P12. Outputs from all of transistors N1, N2, N3, N4, N5, N6 in PTAT slope adjusting unit 412 are combined at a locus 413 for provision to current mirror 421. Current mirror 421 mirrors the combined output received from PTAT slope adjusting unit 412 to output locus 430. Position adjusting arrays 420, 420A, 422, 422A, 428 substantially operate in the same way as described earlier in connection with temperature dependent current generator 310 (FIG. 7). In essence, providing a plurality of position adjusting arrays 420, 420A, 422, 422A, 428 for individual treatment of respective bit positions of PTAT slope adjusting unit 412 permits separate balancing of the current contribution of each individual PTAT-CTAT transistor pair N2-N8, N3-N9, N4-N10, N5-N11, N6-N12. The configuration of the apparatus of the present invention illustrated in temperature dependent current generator 410 is advantageous because temperature dependent current generator 410 may be implemented using less chip area and therefore involves less cost than may be experienced using other configurations described herein.

FIG. 9 is a flow chart illustrating the method of the present invention. In FIG. 9, a method 500 for adjusting a first electrical signal with respect to a second electrical signal begins at a START locus 502. Method 500 continues with the step of, in no particular order: (1) Providing a first converting unit configured for receiving the first electrical signal, as indicated by a block 504. The first converting unit has a plurality of n selectively switchable first binary converting elements. (2) Providing a second converting unit configured for receiving the second electrical signal, as indicated by a block 506. The second converting unit has a plurality of n selectively switchable second binary converting elements. The second converting unit is coupled with an output locus.

Method 500 continues with the step of providing a respective adjusting element coupled with each of a respective selected element of a plurality of selected elements of the plurality of the n switchable first binary converting elements, as indicated by a block 508. Each respective adjusting element is coupled with the output locus.

Method 500 continues with the step of, in no particular order: (1) Operating the plurality of n selectively switchable first binary converting elements to effect digital conversion of the first electrical signal to at least one first representative signal element representing the first electrical signal, as indicated by a block 510. (2) Operating the plurality of n selectively switchable second binary converting elements for effecting digital conversion of the second electrical signal to a second representative signal representing the second electrical signal, as indicated by a block 512. The second converting unit presents the second representative signal to the output locus. (3) Operating each respective adjusting element in cooperation with the respective connected selected element to present a respective corrected first representative signal element to the output locus, as indicated by a block 514. The output locus presents an aggregate output signal including contributions from the second representative signal and each respective corrected first representative signal element presented to the output locus.

Method 500 continues with the step of effecting the adjusting by altering at least one corrected first representative signal element presented to the output locus, as indicated by a block 516. Method 500 terminates at an END locus 518.

It is to be understood that, while the detailed drawings and specific examples given describe preferred embodiments of the invention, they are for the purpose of illustration only, that the apparatus and method of the invention are not limited to the precise details and conditions disclosed and that various changes may be made therein without departing from the spirit of the invention which is defined by the following 

1. An apparatus for adjusting a first electrical signal with respect to a second electrical signal; the apparatus comprising: (a) a first converting unit configured for receiving said first electrical signal; said first converting unit employing a plurality of n selectively switchable first binary converting elements for effecting digital conversion of said first electrical signal to at least one first representative signal element representing said first electrical signal; (b) a second converting unit configured for receiving said second electrical signal; said second converting unit employing a plurality of n selectively switchable second binary converting elements for effecting digital conversion of said second electrical signal to a second representative signal representing said second electrical signal; said second converting unit being coupled with an output locus; said second converting unit presenting said second representative signal to said output locus; and (c) a respective adjusting element coupled with each of a respective selected element of a plurality of selected elements of said plurality of said n switchable first binary converting elements; each said respective adjusting element being coupled with said output locus; each respective adjusting element cooperating with said respective connected selected element to present a respective corrected first representative signal element to said output locus; said output locus presenting an aggregate output signal including contributions from said second representative signal and each said respective corrected first representative signal element presented to said output locus; said adjusting being effected by altering at least one said corrected first representative signal element presented to said output locus.
 2. An apparatus for adjusting a first electrical signal with respect to a second electrical signal as recited in claim 1 wherein said plurality of said n switchable first binary converting elements and said plurality of said n switchable second binary converting elements are each arranged according to significance; and wherein a respective said first binary converting element having a particular significance is switched substantially simultaneously with a respective said second binary converting element having the same particular significance.
 3. An apparatus for adjusting a first electrical signal with respect to a second electrical signal as recited in claim 1 wherein said plurality of selected elements comprises all of said plurality of said n switchable first binary converting elements.
 4. An apparatus for adjusting a first electrical signal with respect to a second electrical signal as recited in claim 1 wherein said adjusting is effected for minimizing said aggregate output signal.
 5. An apparatus for adjusting a first electrical signal with respect to a second electrical signal as recited in claim 4 wherein said first electrical signal represents a first temperature measurement associated with the apparatus, and wherein said second electrical signal represents a second temperature measurement associated with the apparatus.
 6. An apparatus for adjusting a first electrical signal with respect to a second electrical signal as recited in claim 5 wherein said first temperature measurement relates to temperature expressed as proportional to absolute temperature, wherein said second temperature measurement relates to temperature expressed as complementary to absolute temperature, and wherein said adjusting is effected to achieve said minimizing in presence of a predetermined ambient temperature.
 7. An apparatus for adjusting a first electrical signal with respect to a second electrical signal as recited in claim 2 wherein said adjusting is effected for minimizing said aggregate output signal.
 8. An apparatus for adjusting a first electrical signal with respect to a second electrical signal as recited in claim 7 wherein said first electrical signal represents a first temperature measurement associated with the apparatus, and wherein said second electrical signal represents a second temperature measurement associated with the apparatus.
 9. An apparatus for adjusting a first electrical signal with respect to a second electrical signal as recited in claim 8 wherein said first temperature measurement relates to temperature expressed as proportional to absolute temperature, wherein said second temperature measurement relates to temperature expressed as complementary to absolute temperature, and wherein said adjusting is effected to achieve said minimizing in presence of a predetermined ambient temperature.
 10. An apparatus for adjusting a first electrical signal with respect to a second electrical signal at a predetermined ambient temperature; said first electrical signal representing behavior of a first temperature measurement over a first temperature range; said second electrical signal representing behavior of a second temperature measurement over a second temperature range at least overlapping said first temperature range substantially at said predetermined ambient temperature; the apparatus comprising: (a) a first converting unit configured for receiving said first electrical signal; said first converting unit employing a plurality of n selectively switchable first binary converting elements for effecting digital conversion of said first electrical signal to at least one first representative signal element representing said first electrical signal; (b) a second converting unit configured for receiving said second electrical signal; said second converting unit employing a plurality of n selectively switchable second binary converting elements for effecting digital conversion of said second electrical signal to a second representative signal representing said second electrical signal; said second converting unit being coupled with an output locus; said second converting unit presenting said second representative signal to said output locus; and (c) a respective adjusting element coupled with each of said plurality of said n switchable first binary converting elements; each said respective adjusting element being coupled with said output locus; each respective adjusting element cooperating with said respective connected converting element to present a respective corrected first representative signal element to said output locus; said output locus presenting an aggregate output signal including contributions from said second representative signal and each said respective corrected first representative signal element presented to said output locus; said adjusting being effected by altering at least one said corrected first representative signal element presented to said output locus.
 11. An apparatus for adjusting a first electrical signal with respect to a second electrical signal at a predetermined ambient temperature as recited in claim 10 wherein said plurality of said n switchable first binary converting elements and said plurality of said n switchable second binary converting elements are each arranged according to significance; and wherein a respective said first binary converting element having a particular significance is switched substantially simultaneously with a respective said second binary converting element having the same particular significance.
 12. An apparatus for adjusting a first electrical signal with respect to a second electrical signal at a predetermined ambient temperature as recited in claim 10 wherein said adjusting is effected for minimizing said aggregate output signal at said predetermined ambient temperature.
 13. An apparatus for adjusting a first electrical signal with respect to a second electrical signal at a predetermined ambient temperature as recited in claim 10 wherein said first temperature measurement relates to temperature expressed as proportional to absolute temperature, wherein said second temperature measurement relates to temperature expressed as complementary to absolute temperature, and wherein said adjusting is effected to achieve said minimizing in presence of a predetermined ambient temperature.
 14. An apparatus for adjusting a first electrical signal with respect to a second electrical signal at a predetermined ambient temperature as recited in claim 11 wherein said adjusting is effected for minimizing said aggregate output signal at said predetermined ambient temperature.
 15. An apparatus for adjusting a first electrical signal with respect to a second electrical signal at a predetermined ambient temperature as recited in claim 11 wherein said first temperature measurement relates to temperature expressed as proportional to absolute temperature, wherein said second temperature measurement relates to temperature expressed as complementary to absolute temperature, and wherein said adjusting is effected to achieve said minimizing in presence of a predetermined ambient temperature.
 16. An apparatus for adjusting a first electrical signal with respect to a second electrical signal at a predetermined ambient temperature as recited in claim 14 wherein said first temperature measurement relates to temperature expressed as proportional to absolute temperature, wherein said second temperature measurement relates to temperature expressed as complementary to absolute temperature, and wherein said adjusting is effected to achieve said minimizing in presence of a predetermined ambient temperature.
 17. A method for adjusting a first electrical signal with respect to a second electrical signal; the method comprising the steps of: (a) in no particular order: (1) providing a first converting unit configured for receiving said first electrical signal; said first converting unit having a plurality of n selectively switchable first binary converting elements; and (2) providing a second converting unit configured for receiving said second electrical signal; said second converting unit having a plurality of n selectively switchable second binary converting elements; said second converting unit being coupled with an output locus; (b) providing a respective adjusting element coupled with each of a respective selected element of a plurality of selected elements of said plurality of said n switchable first binary converting elements; each said respective adjusting element being coupled with said output locus; (c) in no particular order: (1) operating said plurality of n selectively switchable first binary converting elements to effect digital conversion of said first electrical signal to at least one first representative signal element representing said first electrical signal; (2) operating said plurality of n selectively switchable second binary converting elements for effecting digital conversion of said second electrical signal to a second representative signal representing said second electrical signal; said second converting unit presenting said second representative signal to said output locus; and (3) operating each respective adjusting element in cooperation with said respective connected selected element to present a respective corrected first-representative signal element to said output locus; said output locus presenting an aggregate output signal including contributions from said second representative signal and each said respective corrected first representative signal element presented to said output locus; and (d) effecting said adjusting by altering at least one said corrected first representative signal element presented to said output locus.
 18. A method for adjusting a first electrical signal with respect to a second electrical signal as recited in claim 17 wherein said plurality of said n switchable first binary converting elements and said plurality of said n switchable second binary converting elements are each arranged according to significance; and wherein a respective said first binary converting element having a particular significance is switched substantially simultaneously with a respective said second binary converting element having the same particular significance.
 19. A method for adjusting a first electrical signal with respect to a second electrical signal as recited in claim 17 wherein said first temperature measurement relates to temperature expressed as proportional to absolute temperature, wherein said second temperature measurement relates to temperature expressed as complementary to absolute temperature, and wherein said adjusting is effected to achieve said minimizing in presence of a predetermined ambient temperature.
 20. A method for adjusting a first electrical signal with respect to a second electrical signal as recited in claim 18 wherein said first temperature measurement relates to temperature expressed as proportional to absolute temperature, wherein said second temperature measurement relates to temperature expressed as complementary to absolute temperature, and wherein said adjusting is effected to achieve said minimizing in presence of a predetermined ambient temperature. 